Broadcom
Mixed Signal Design Intern
Huawei Technologies
Design Engineer Intern
China Educational Technology Initiative (CETI) MIT MISTI China Program
CETI Program Intern, Academic and Cultural Exchange Course Instructor
Xilinx
System and Circuit Design Intern
Analog Devices
MIT VI-A Program Design Intern
Xilinx
Staff Analog and Mixed Signal Design Engineer
Texas Instruments
System Design Intern
Xilinx
Senior Staff Design Engineer
Cisco Tsinghua Joint Lab for Green Technology
Summer Intern and Researcher
Massachusetts Institute of Technology
Stanford University
