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Dhruv Saxena

UVM-based Verification IP for AXI4-Lite

United States

Work:
Employment History of Dhruv Saxena

San Jose State University

UVM-based Verification IP for AXI4-Lite


LR Automation

Automation Engineer Intern


Samsung Semiconductor

Senior Design Verification Engineer


Qualcomm

Design Verification Engineer


Design of a Data Scrambler

Employee


Siddhartha Enterprises

Manager


Scalable Systems Research Labs Inc.

Asic Design Engineer


LG Electronics

Production Engineering DDM Intern


Candidate Pool

ASIC Design Engineer Intern


Udemy

Design Verification Engineer


Integra Technologies Inc.

Asic Design Verification Engineer

Schools:
Schools Attended by Dhruv Saxena

Maharshi Dayanand University


San Jose State University

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